1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to a method of reducing silicon damage that occurs during shallow trench isolation (STI) CMP process around a laser mark region of a semiconductor wafer.
2. Description of the Prior Art
As known in the art, modern semiconductor integrated circuits are fabricated at the surface of a wafer of semiconductor material such as single-crystal silicon. Each circuit, which is referred to as a “die” when in chip form, is at a position within an array of die at the wafer surface, so as to be fabricated simultaneously with the other die on that wafer. Since some manufacturing processes, such as thermal oxide growth, cleanups, and the like are performed simultaneously for multiple wafers, the wafers are also generally grouped into lots during the manufacturing processes. Other processes, such as photolithography, plasma etching, and the like are generally performed on a wafer-by-wafer basis.
In the manufacture of integrated circuits, it has become commonplace to mark wafers with some type of identifier, generally a lot identifier and a wafer identifier. These identifiers are conventionally marked on the front surface of the wafer (i.e., the wafer surface at which the integrated circuits are being formed). A typical method of marking the lot identifier on a semiconductor wafer is by laser marking, where the laser locally melts the semiconductor in a pattern corresponding to the lot number and wafer number.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a plan view showing laser mark region 12, wafer edge exposure (WEE) and edge bead removal (EBR) regions on a typical wafer 10. FIG. 2 is an enlarged view showing portions of the integrated circuit die areas 22 and wafer 10 adjacent to the laser mark region 12 of FIG. 1. As shown in FIG. 1 and FIG. 2, the laser marking of wafer 10 is conventionally made in a notched region (hereinafter referred to as “laser-marking region”) 12 at the front surface of the wafer 10. Typically, the laser-marking region 12 bounds on the scribe line 24 that surrounds each integrated circuit die area 22, and the boundary between the laser-marking region 12 and the scribe line 24 is about 6.5 millimeters (mm) away from the wafer rim 40. The laser-marking region 12 is disposed at the wafer edge so as not to disrupt the formation of integrated circuits. Typically, a wafer notch 14 is formed within the laser-marking region 12.
In FIG. 2, ordinarily, an EBR border 30, which is about 1.5 mm away from the wafer rim 40, and the WEE border 20, which is about 2.5 mm away from the wafer rim 40 are provided. It is known that photoresist and anti-reflective coating (if applied) within an annular peripheral region between the EBR border 30 and the wafer rim 40 are typically chemically washed away during lithographic process for reducing contamination risk. Photoresist within an annular peripheral region or WEE region between the WEE border 20 and the wafer rim 40 is exposed to light and then removed from the wafer periphery after development. Further, integrated circuit components, features or patterns are typically not formed in the redundancy substrate area 26 at the left-hand side of the laser mark region 12 and in the redundancy substrate area 28 at the right-hand side of the laser mark region 12.
Please refer to FIGS. 3-7. FIGS. 3-7 are schematic cross-sectional diagrams showing portions of the integrated circuit die area 22 and the laser-marking region 12 of the wafer 10 along line I-I of FIG. 2 during the fabrication of shallow trench isolation (STI) regions in accordance with the prior art method. In the fabrication of STI regions, a so-called active area (AA) photoresist is patterned and used as a trench dry etching mask. As shown in FIG. 3, a laser marking feature 50, generally a lot identifier and a wafer identifier, is provided in the semiconductor substrate 100 within the laser-marking region 12 of the wafer 10. A pad oxide layer 62 is formed over the semiconductor substrate 100. A pad nitride layer 64 is then deposited on the pad oxide layer 62.
As shown in FIG. 4, using conventional lithographic process, a layer of AA photoresist pattern 70 is formed on the pad nitride layer 64. The AA photoresist pattern 70 comprises openings 72 that expose STI trench areas within the integrated circuit die area 22 to be etched into the semiconductor substrate 100, and an opening 74 that exposes the entire laser-marking region 12. The entire laser-marking region 12 is opened along with the previously described WEE region.
As shown in FIG. 5, using the AA photoresist pattern 70 as an etching hard mask, a dry etching process is carried out to etch the exposed pad nitride layer 64, pad oxide layer 62 and semiconductor substrate 100 through the openings 72 and 74 so as to form STI trenches 82 within the integrated circuit die area 22 and trench 84 within the laser-marking region 12. After this, the remaining AA photoresist pattern 70 is stripped off. As shown in FIG. 6, trench fill material 88 such as chemical vapor deposition (CVD) oxide is deposited over the semiconductor substrate 100 to fill the trenches 82 and 84.
As shown in FIG. 7, using the pad nitride layer 64 as a polish stop, a conventional STI chemical mechanical polishing (CMP) process is carried out to remove excess trench fill material 88 outside the STI trench. During the STI CMP process, it is desirable to completely remove the trench fill oxide disposed directly above the pad nitride layer 64 (or referred to as “active-area oxide”) such that the pad nitride layer 64 can be stripped off in the following nitride strip process.
Insufficient active-area oxide removal usually hampers the removal of the pad nitride layer 64, potentially causing yield degradation. To ensure the complete removal of the trench fill oxide disposed directly above the pad nitride layer 64, an over-polish or etching step is usually carried out. However, such over-polish or etching leads to defects such as excessive pad nitride erosion, trench oxide loss, scratches and silicon damage as indicated by numeral number 92. In practical cases, severe silicon damage has been observed in the dashed line region 90 as specifically indicated in FIG. 2.